This invention relates to information processing systems and methods for manipulating and resolving data, and particularly to computer systems and methods. The invention is particularly useful for building circuits, and for building processors utilizing a plurality of such circuits.
Traditional electronic logic circuits are composed of continuously acting logic elements which are continuously asserting a potentially legitimate result. When new input data is presented to a circuit, the result asserted by the circuit might change several times before settling to the correct result. In general it is not possible to determine, in terms of the circuit output itself, when the correct result is asserted by the circuit.
The determination of completion has generally been accomplished by a representation external to the circuit, most often a system clock. Other types of external representations have also been used, such as a delay line associated with each circuit. Such external systems are provided to indicate when the output of the circuit is VALID. They do so by allowing sufficient time for the logic circuit to settle to a correct result before declaring the result values VALID.
External timing of the logic circuit requires that the control and logic representations be carefully engineered to coordinate their timing characteristics. Because they must be coordinated or synchronized, such systems are typically referred to as synchronous systems. In the case of a system clock, the circuit has to be carefully designed so that it is assured of settling to a correct result within one clock period. Similarly, a delay line must be long enough to accommodate the timing of the circuit and it must also be guaranteed that it's delayed control signal will be stable for a long enough time. Such synchronization considerations place significant complications on system design.
The existing technology of speed independent or Muller circuits does not postulate a NULL value integrated into the primitive transform elements. It relies instead on Boolean logic gates carefully arranged to provide the whole circuit with a specific resolution behavior. This cannot, however, eliminate all possible hazards due to circuit element delays. Transmission elements can introduce delays that could cause incorrect function of the circuit. The existing technology is not logically complete in that physical timing characteristics of the circuit element still have to be considered in any circuit design.
Speed independent circuits put the burden of completion integrity on the configuration of the circuit itself and cannot achieve a purely logical expression of the circuit. The NULL convention puts the burden of completion integrity on the primitive transform elements. This allows a purely logical expression of a circuit quite independent of the physical timing behavior of all circuit elements.
A known concept using a non-data representation as a control means is the spacer code of dual rail encoding associated with speed independent circuits. Dual rail encoding, however, is an interface signaling protocol between circuits and is not a concept associated with the internal organization of the circuits themselves.
Despite the need for a system or environment in the art which enables autonomously acting and coordinated logic circuits to implement independently acting and locally controlled process representations without the need for external control representations, and which overcomes the limitations and problems of the prior art, none insofar as is known has been proposed or developed.
Accordingly, it is an object of the present invention to provide an information processing system and method for manipulating and resolving data. Another object of the invention is to provide a system and method which is useful for constructing information processing units and members such as circuits and gates and for constructing configurable processors utilizing a plurality of such circuits and gates.
Yet another object of this invention is to provide a system and method which enables processors having autonomously acting and coordinated logic circuits to implement independently acting locally controlled process representations without the need for external control representations. A further object of the invention is to provide a system and method as described above which utilizes the representation of control as a value with respect to the logic circuits and gates themselves.
Still another object of the invention is to provide a system and method of utilizing a null convention in logic and processor design and function.